1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
FIG. 7 is a block diagram showing a semiconductor device. In the semiconductor device 100, a processor chip 110 and a memory chip 120 are connected to each other through a communication path 130 provided in a substrate or a system board of a semiconductor package. The processor chip 110 is what is known as a multicore processor, which includes a plurality of processor cores 112.
The semiconductor device 100 thus including the multicore processor (processor chip 110) is expected to exhibit excellent performance through operating the plurality of processor cores 112 in parallel.
In the semiconductor device 100, however, the plurality of processor cores 112 receives and outputs a signal through an I/O region provided in common on the processor chip 110. Accordingly, despite the parallel operation of the processor cores 112, the communication with the memory chip 120 is not efficiently performed, which spoils the high operation speed which would otherwise be achieved, thereby restricting the performance of the semiconductor device 100. Moreover, the communication between the processor chip 110 and the memory chip 120 is made through the communication path 130 provided in the substrate or the system board of the semiconductor package, in other words, through a long distance. Such configuration may incur degradation in performance of the semiconductor device 100, originating from a delay in communication.
A solution of such drawback of the delay in communication would be providing a memory region 144 in a semiconductor chip 140 including a processor core 142, as shown in FIG. 8, to thereby improve the communication speed between the processor core 142 and the memory region 144. Such structure, however, inevitably leads to an increase in area of the semiconductor chip 140, in proportion to the footprint of the memory region 144. Besides, in this case a sufficient capacity of the memory region 144 may not always be secured, because increasing the capacity of the memory region 144 incurs a further increase in area of the semiconductor chip 140. Besides, providing the plurality of processor cores offers no solution of the problem that the high operation speed, expected from operating the plurality of processor cores in parallel, cannot be achieved.
Non-patented document 1 cited below suggests a structure in which a memory chip including a via penetrating through a silicon substrate is stacked on a processor chip including a plurality of processor cores, by means of bumps provided therebetween. Such structure allows allocating a large-capacity memory to each processor core. In this case, the communication between the processor core and the memory chip is performed by the intermediation of the via penetrating through the silicon substrate. In other words, the communication between the processor core and the memory is made by the intermediation of the through-silicon via formed in the memory chip. On the sidewall of the through-silicon via formed in the memory chip, an insulating layer is provided for insulation from the silicon. Accordingly, the through-silicon via formed in the memory chip (in the silicon substrate) has large parasitic capacitance, which disturbs increasing the speed of the communication. Also, in order to increase the number of communication paths from the processor, the number of through-silicon vias in the memory chip has to be increased. Further, devices such as transistors cannot be formed in a region where the through-silicon via is provided, which resultantly leads to an increase in cost of the memory chip, per unit capacity.
Reference to the foregoing technique can be found, for example, in JP-A No. 2006-19433, JP-A No. 2003-60153, JP-A No. 2001-24150, and JP-A No. 2001-24089, and also in the websites cited below.
[Patented document 1] JP-A No. 2006-19433
[Patented document 2] JP-A No. 2003-60153
[Patented document 3] JP-A No. 2001-24150
[Patented document 4] JP-A No. 2001-24089
[Non-patented document 1]
http://techon.nikkeibp.co.jp/article/NEWS/20060927/121563/
[Non-patented document 2]
http://japan.cnet.com/news/ent/story/0,2000056022, 20254608,00.htm
As stated above, in semiconductor devices including a processor chip having a plurality of processor cores, sufficiently high communication speed between each of the processor cores of the processor chip and a memory chip has not been achieved, despite that parallel operation of the processor cores is expected to achieve a significant increase in processing speed.
This is also the case with semiconductor chips including a plurality of functional blocks. To be more detailed, in the semiconductor chip including the plurality of functional blocks, an I/O region has to be shared among the functional blocks, which leads to such drawbacks as degradation in efficiency of communication with another semiconductor chip, delay in communication originating from a long communication distance between each functional block and another semiconductor chip, and delay in communication originating from parasitic capacitance in a communication path, such as the through-silicon via, for another semiconductor chip.
In view of the foregoing problems, an object of the present invention is to provide a semiconductor device including a semiconductor chip having a plurality of functional blocks, capable of increasing communication speed between each of the functional blocks and another semiconductor chip.